----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:36:25 04/25/2012 
-- Design Name: 
-- Module Name:    score_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity score_counter is
	Port (clk : in std_logic;
		update_count : in std_logic;
		count : out std_logic_vector(3 downto 0));
end score_counter;

architecture Behavioral of score_counter is

	signal count_internal : std_logic_vector(3 downto 0) := "0000";

begin

	process(clk)
	begin
		if rising_edge(clk) then
			if update_count = '1' then
				if count_internal = "1001" then
					count_internal <= "0000";
				else
					count_internal <= std_logic_vector(unsigned(count_internal)+1);
				end if;
			else
				count_internal <= count_internal;
			end if;
		end if;
	end process;
	
	count <= count_internal;

end Behavioral;

